The present invention relates to a semiconductor device having function storing information and a manufacturing method of the semiconductor device, particularly to improvement of such functions as re-writing, reading and storing information in the semiconductor device.
DRAM (Dynamic Random Access Memory) is a memory device comprising a semiconductor for storing information and has been hitherto widely used. Storage elements (memory cells) forming DRAM each typically comprises a storage capacitance and a switching MOS (Metal-Oxide-Semiconductor) FET, so that reading stored data is performed by taking out in the form of digital signals "0" or "1" through bit lines a specific voltage corresponding to a state of charges accumulated in the storage capacitance of a selected memory cell. The stored data in DRAM disappears instantly when a power supply is stopped, i.e., the stored data is volatile. The stored data of DRAM is read out "destructively" to then be no longer exist in the device, whereby necessitating refreshing of data (writing again the data read out).
Flash-EEPROMs (Electrically Erasable Programmable Read Only Memories) is a nonvolatile memory characterized in that data stored in the device is kept alive even when a power supply is stopped. Each memory cell of flash-EEPROMs comprises a MOSFET having a so-called stacked gate structure including a control gate electrode, a semiconductor substrate and a floating-gate electrode provided therebetween. Data storage is performed by use of a change of threshold in MOSFETs corresponding to specific amounts of charges accumulated in the floating gate. Writing data is carried out by feeding charges (electrons generally) from the semiconductor substrate into the floating gate, using that hot carrier generated by applying high voltage to drain regions gets over an energy barrier formed with gate oxide, or that gate oxide is applied with a high electrical field to allow F-N (Fowler-Nordheim) tunneling current to flow. Erasing data is performed by applying to the gate oxide a high electrical field in the opposite direction to the above so as to draw charges from the floating gate to the semiconductor substrate through the F-N tunneling. The flash EEPROM does not require refreshing of data as in DRAMs but it takes longer time to write and erase data largely differently than DRAMs.
Another nonvolatile memory is NV-DRAM (Non-Volatile DRAMs) whose memory cells each typically comprises a MFS (Metal-Ferrodielectric-Semiconductor) FET using a ferroelectric substance as gate insulator, wherein ionic polarization in the ferroelectrics is changed corresponding to orientation of application of electrical field so as to change threshold of the MFSFET, thereby storing data. Japanese Unexamined Patent Application No. 4-97564(1992) discloses another type of NV-DRAM, i.e, a semiconductor device using "electronic dipole" polarization in place of the ionic polarization in ferroelectrics above wherein as shown in FIGS. 24 and 25 a plurality of active regions provided among the insulator barriers each corresponds to the respective crystal lattice made of the ferroelectrics and an applied electrical field allows conductive carriers to pass to and from through the tunneling barriers (formed in the active regions) and be localized, thereby storing data. The NV-DRAMs are essentially nonvolatile due to a memorizing function by polarization but require data to be read "destructively" similarly to DRAMs as foregoing, necessitating refreshing of data when read.
Generally, an ideal semiconductor memory applicable to electronic equipments in the future needing high speed operation, low power consumption, portability and compactness is a combination of merits of DRAMs and flash EEPROMs and should satisfy the following requirements.
(a) Writing and erasing as well as reading are performed at a high speed as several hundred nsec. or lower, which is the merit of DRAMs but not of flash EEPROMs. PA1 (b) The memory has the maximum number of writing to enable continuous writing of data for 10 years (general life expectancy in industries), which is the merit of DRAMs but not of flash EEPROMs. PA1 (c) Data once stored is held without power supply for 10 years in an electric field which is generated internally in the device when a carrier exists at a position, and orientation of the electric field tends to cause the carrier to flow away from the position, which is the merit of flash EEPROMs but not of DRAMs. PA1 (d) The device has no "destructive" data reading, i.e., no necessity of refreshing data whenever read for the purpose of low power consumption, which is the merit of flash EEPROMs but not of DRAMs. PA1 (A) Writing and erasing need high current Itunn about 1A/cm2, and applied voltage (so-called writing voltage) is preferably about .+-.20 V or less for the purpose of low power consumption and in view of specific design of integrated circuits. PA1 (B) It is required to enable re-writing data more than at least 10.sup.16 times (the number 2 or 3 figures lower is acceptable, for example, 10.sup.14, in case of no "destructive" reading). PA1 (C) In holding data, the current Itunn should be very much low to be about 10.sup.16 A/cm2 or less within the voltage range of at least .+-.0.5 V to .+-.1 V corresponding to the electric field generated in existence of carriers. PA1 (D) To eliminate the "destructive" reading, a practical working voltage range for reading is preferably at least .+-.1 V to .+-.2 V (this feature is incidental to the item (C) since other features than the working voltage range are the same as of the item (C)).
Nonvolatile memories developed in recent years use MIS type semiconductors having gate insulator about 10 nm thick and employs a data storing system using existence/non-existence of carriers in the order at least of 10.sup.12 /cm2 in the insulator regions. Transfer of carriers is performed generally by tunneling barriers provided in the insulator regions. Assuming the current in this instance is Itunn, the foregoing requirements (a) to (d) are referred to more concretely as follows.
As seen from the above, the ideal tunneling barriers should satisfy the strict requirements that resistance is variable over about 15 figures and the barrier has high resistance equal to insulators in a low electric field. The conventional art does provide neither any semiconductor memories which could satisfy all the above requirements nor nonvolatile semiconductor memories satisfying only the above requirement (A) or those (B) and (C). DRAMs which concern the "destructive" reading need to have refreshing data whenever read. Additionally, charges accumulated in the storage capacitances leak gradually to be lost, so that DRAMs require to have periodically refreshing data, even when not read at all, at a predetermined time interval (the so-called refreshing time every 1 msec to 100 msec). Hence, DRAMs have the defects that stored data is volatile and the device needs large power consumption.
Flash EEPROMs hold data even when power supply is stopped, not necessitating the data-refreshing operation. The semiconductor device however requires to be applied internally, particularly at the gate oxide, with a quite large electric field (10 MV/cm2 or more, generally, near the maximum dielectric breakdown field of silicon oxide). Hence, flash EEPROMs are hard to achieve reliability and are limited in the feasible re-writing number to 10.sup.4 to 10.sup.5 at the maximum. Additionally, electric field and current applied upon writing and erasing data have certain upper limits in relation to the insufficient reliability, resulting in that time required for writing and erasing data is quite longer (several 10 .mu.sec and several 10 msec typically for writing and erasing, respectively) widely different from several 10 nsec as of DRAMs.
Furthermore, flash EEPROMs use the stacked gate structure, necessitating higher writing and erasing voltages corresponding to the coupling ratio of specific capacitances. Stacked gate type flash EEPROMs including gate oxide 8 nm thick having E4 type energy level properties, as exemplified in FIG. 4, require to be applied with high voltage about 15 to 20 V for writing and erasing data. Hence, the device when used as an IC memory element requires an additional generator circuit for the above high voltage and an extra power consumption to the extent of higher voltage. Also, a typical data-writing system using hot carriers has such defect of further larger power consumption for writing data due to low feeding efficiency of hot carriers into the floating gate.
MFSFETs, the typical NV-DRAM, has the problems in the material itself of ferroelectrics and has not yet been put into practical use. The ferroelectrics when used in MFSFET is required to be thinner to several 100 nm or less, so that the ionic polarization becomes quite small insufficient for practical use; a stable and favorable interface with the semiconductor sufficient for practical use as FETs is hard to obtain; specific processes before and after the film formation process are restricted in various conditions by the ferroelectric materials having high reactivity; and there additionally occurs the problem of the so-called film fatigue that the ionic polarization lowers following the specific numbers of writing data (the maximum number of writing more or less 10.sup.10 times typically), and dielectric breakdown in the film.
The semiconductor device disclosed in the Japanese Unexamined Patent Application No. 4-97564(1992) provides, as shown in FIG. 22 and 28 and in the claims, in the insulator barriers a plurality of active regions each corresponding to the respective crystalline lattice made of the ferroelectrics, and in each active region a tunneling barrier. Due to the latter feature, this device does however not satisfy the foregoing requirements for the ideal semiconductor memory. The energy level properties of E1 type shown in FIG. 4 explains the case using the structure shown in the Japanese publication and a most simple feature having only one active region, wherein the peripheral barrier regions sandwitching the active region are 6 nm thick to prevent conductive carriers existing therein from leaking to the outside through a direct tunneling, and a tunneling barrier 3 nm thick causing the direct tunneling uses energy barriers .DELTA.Et of 1.4 eV and 3.2 eV. It will be appreciated from the drawing that even with the energy barrier 3.2 eV rather higher among the practical barriers, the current Itunn in the low voltage range upon data hold is extremely high, resulting in that the device is quite hard to satisfy both the requirements (C) and (D). Using the lower barrier 1.4 eV further increases the current Itunn in the low voltage range upon data hold. In the low voltage range a current from the direct tunneling is dominant, while in the range of 10.sup.-2 A/cm2 or more for high speed writing the tunneling barrier film is applied with a high electric field near 10 MV/cm to allow a F-N tunneling current component is rather dominant. That is, it is seen from the drawing that even with a thin tunneling barrier causing the direct tunneling the tunneling barrier is applied with a high electric field substantially equal to that of the flash EEPROM upon the high speed writing. Hence, the semiconductor device disclosed in the Japanese publication is hard also to satisfy the requirement (B) since the maximum number of writing is substantially limited as in the flash EEPROMs. The substantially same conclusion should be obtained with different values of the tunneling barrier thickness, energy barrier .DELTA.Et and the peripheral barrier regions thickness from those referred to in the above example. Also, provision of a plurality of active regions other than the single active region as above should deduce the same conclusion. In brief, the semiconductor device shown in the Japanese publication does not satisfy at least the requirement (A), similarly the requirement (B), and further both of those (C) and (D) at a time. Additionally, the semiconductor device utilizes the polarization effect with "electric dipole" as shown in FIGS. 22 and 23 and in the claims. Thus, the active regions in the insulator barrier should be plural. In case that thickness of the barrier regions, i.e, the peripheral barrier region and tunneling barrier 3 are 6 nm and 3 nm as above, the total thickness of the barrier regions will be 24 nm and 33 nm, or more, for the cases using the least 2 or 3 active regions, respectively. The actual thickness of the barrier regions will be larger in fact with additional thickness of the low barrier regions in the active regions. In view of the fact that MIS type nonvolatile memories at present or in the near future require the gate insulator to be thinner to 10 nm for the purpose of realization of micronization and very large scale integration, the substantially thick insulator regions of the semiconductor device in the Japanese Publication are essentially not suitable for the devices of large scale integration.